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ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 1 mc008-0c 11/27/2001 icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. cmos single chip 8-bit microcontroller with 8(4)-kbytes of flash features ? 80c52(51) based architecture 8(4)-kbytes flash memory with fast-pulse programming algorithm and software protection 256 x 8 ram (128x8 ram) three (two)16-bit timer/counters full duplex serial channel boolean processor four 8-bit i/o ports, 32 i/o lines memory addressing capability ? 64k rom and 64k ram program memory lock ? lock bits (3) power save modes: ? idle and power-down eight interrupt sources most instructions execute in 0.3 s cmos and ttl compatible maximum speed: 40 mhz @ vcc = 5v packages available: ? 40-pin dip ? 44-pin plcc ? 44-pin pqfp general description the icsi ic89c52(51)a is a high-performance micro- controller fabricated with high-density cmos technology. the cmos ic89c52a is functionally compatible with the nmos intel 8052(51), philips? 80c52(51) micro controller. the ic89c52(51)a contains a 8k (4k) x 8 flash; a 256 x 8 ram (128 x 8 ram); 32 i/o lines for either multi- processor communications; i/o expansion or full duplex uart; three (two) 16-bit timers/counters; a six-source (five-source), two-priority-level, nested interrupt structure; and on chip oscillator and clock circuit. the ic89c52(51) a can be expanded using standard ttl compatible memory. figure 1. ic89c52(51)a pin configuration: 40-pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 t2/p1.0 t 2ex/p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 gnd vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp ale/pro g psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8
ic89c52(51)a 2 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 top view figure 2. ic89c52(51)a pin configuration: 44-pin plcc wr/p3.6 rd/p3.7 xtal2 xtal1 gnd nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp nc ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 index 43 65 2144 18 19 20 21 22 23 24 43 42 41 40 25 26 27 28
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 3 mc008-0c 11/27/2001 figure 3. ic89c52(51)a pin configuration: 44-pin pqfp wr/p3.6 rd/p3.7 xtal2 xtal1 gnd nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc v cc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp nc ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 38 12 13 14 15 16 17 18 37 36 35 34 44 43 42 41 40 39 19 20 21 22
ic89c52(51)a 4 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 figure 4. ic89c52(51)a block diagram pcon scon tmod tcon t2con th0 tl0 th1 tl1 th2 tl2 rcap2h rcap2l sbuf ie ip interrupt block serial port block timer block p3 drivers p3 latch psw timing and control oscillator xtal2 xtal1 instruction register p3.0-p3.7 p1 drivers p1 latch dptr buffer pc incrementer program counter program address register p1.0-p1.7 p2.0-p2.7 p0.0-p0.7 psen ale/prog rst ea/vpp tmp2 alu acc stack point b register vcc gnd ram addr register p2 latch p0 latch p2 drivers p0 drivers address decoder & 256 bytes ram address decoder & 8k flash 3 lock bits tmp1
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 5 mc008-0c 11/27/2001 table 1. detailed pin description symbol pdip plcc pqfp i/o name and function ale/ prog 30 33 27 i/o address latch enable: output pulse for latching the low byte of the address during an address to the external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input ( prog ) during flash programming. ea /v pp 31 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 1fffh . if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 1fffh. this also receives the 12v programming enable voltage (v pp ) during flash programming. p0.0-p0.7 39-32 43-36 37-30 i/o port 0: port 0 is an 8-bit open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pullups when emitting 1s. port 0 also receives the command and code bytes during programmable memory programming and outputs the code bytes during program verification. external pullups are required during program verification. p1.0-p1.7 1-8 2-9 40-44 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal 1-3 pullups. port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). the port 1 output buffers can sink/source four ttl inputs. port 1 also receives the low-order address byte during flash programming and verification. 1240i t2(p1.0): timer/counter 2 external count input.(ic89c52a only) 2341i t2ex(p1.1): timer/counter 2 trigger input.(ic89c52a only) p2.0-p2.7 21-28 24-31 18-25 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). port 2 emits the high order address byte during fetches from external pro- gram memory and during accesses to external data memory that used 16-bit addresses (movx @ dptr). in this application, port 2 uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri [i = 0, 1]), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order bits and some control signals during flash programming and verification. p2.6 and p2.7 are the control signals while the chip programs and erases.
ic89c52(51)a 6 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 symbol pdip plcc pqfp i/o name and function p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pullups. port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). port 3 also serves the special features of the ic89c52(51)a, as listed below: 10 11 5 i rxd (p3.0): serial input port. 11 13 7 o txd (p3.1): serial output port. 12 14 8 i int0 int0 int0 int0 int0 (p3.2): external interrupt 0. 13 15 9 i int1 int1 int1 int1 int1 (p3.3): external interrupt 1. 14 16 10 i t0 (p3.4): timer 0 external input. 15 17 11 i t1 (p3.5): timer 1 external input. 16 18 12 o wr wr wr wr wr (p3.6): external data memory write strobe. program control signal while the chip programs and erases. 17 19 13 o rd rd rd rd rd (p3.7): external data memory read strobe. program control signal while the chip programs and erases. psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. psen is an input control signal while memory program and verification. rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running resets the device. an internal resistor to vss permits a power-on reset using only an external capacitor. a small internal resistor permits power-on reset using only a capacitor connected to vcc. rst is an input control signal during memory program and verification. xtal 1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal 2 18 20 14 o crystal 2: output from the inverting oscillator amplifier. gnd 20 22 16 i ground: 0v reference. vcc 40 44 38 i power supply: this is the power supply voltage for operation. table 1. detailed pin description ( cont i nued)
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 7 mc008-0c 11/27/2001 figure 5. programming interface programming the ic89c52(51)a: the ic89c52(51)a is normally shipped the on-chip flash memory array in the erased state (i.e. contents=ffh) and ready to be programmed. the ic89c52(51)a is programmed byte-by-byte in programming mode. before the on-chip flash code memory can be re-programmed, the entire memory array must be erased electrically. programming interface: some conditions must be satisfied before entering the programming mode. the conditions are listed following. 1. rst is high level 2. psen is low level 3. p3.6 and p3.7 is high level the interface-controlled signals are matched these conditions, then the ic89c52(51)a will enter received command mode. the flash command is accepted by the flash command decoder in command received mode. the programming interface is listed in figure 5. vss rst psen ale/prog ea/vpp p2.6 p2.7 p3.6 p3.7 xtal1 h l prog pulse 12v/h command write output enable h h 1-12mhz clock vcc ic89c52a/51a 10k vcc d7-d0 p0 p1 a7-a0 p2.4-2.0 a12-a8 operating description the detail description of the ic89c52(51)a included in this description are: ? memory map and registers ? timer/counters ? serial interface ? interrupt system ? other information the detail information desription of the ic89c52(51)a refer to ic80c52/32 data sheet
ic89c52(51)a 8 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 flash command definitions bus first bus cycle second bus cycle cycle operation address data vpp operation address data vpp normal verify (1) (n+1) (2) p2.6 x 00h h p2.7 low sa (3) sd (3) h read signature byte 4 p2.6 x 90h h p2.7 low 30h d5h 31h 52h 32h 55h/aah program code memory 2 p2.6 x 40h h prog pa (3) pd (3) 12v/h program verify (1) (n+1) (2) p2.6 x c0h h p2.7 low sa pvd (3) h program lock bit 1 2 p2.6 x 60h h prog x d0h 12v/h program lock bit 2 2 p2.6 x 70h h prog x d0h 12v/h program lock bit 3 2 p2.6 x 80h h prog x d0h 12v/h chip erase 2 p2.6 x 20h h prog x d0h 12v/h erase verify (1) (n+1) (2) p2.6 x a0h h p2.7 low ea (3) evd (3) h note: 1. normal verify: internal flash sense amplifier uses the same threshold as instruction executing threshold. program verify: the flash sense amplifier applies an internally generated higher margin voltage to the addressed byte. if a comparison between the programmed byte and the true data is successful, there is a margin exists in the programmed data. erase verify: the flash sense amplifier applies an internally generated lower margin voltage to the addressed byte. reading ffh from the addressed byte indicates that all bits in the bytes are erased. 2. to verify n bytes data. 3. sa = selected address of memory location to be read except program or erase verify. sd = data read from location sa with normal verification threshold. pa = address of memory location to be programmed. pd = data to be programmed at location pa. pvd = data read from location pa during program verify. ea = address of memory location to be read during erase verify. evd - data read from location ea during erase verify. programming core memory every code byte in the flash array can be written and the entire array can be erased using the appropriate command from port 0 by programmer or application system. the program/erase are two-cycle operations. the first cycle is command write cycle; the command 40h is written by p2.6 falling and rising edges. the command would be held a stable value within p2.6 low state. the command decoder enables programming flag after the first cycle is completion, then the internal programming flag is set. rising edge of prog will clear internal programming flag, so the programming command must be presented every programming cycle. the second cycle is real flash programming cycle. the programming address and data are latched at prog falling edge, the programming time is controlled by low time of prog . the programming flag is cleared at prog rising edge in the second cycle. programming address range is from 0 to 1fffh. ic89c52(51)a programming range is from 0 to 1fffh, but the program counter will jump to external menory while mcu executing the address is excess 0fffh. the ic89c52(51)a code memory programming now is described in figure 6.
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 9 mc008-0c 11/27/2001 program verify if lock bits lb2 and lb3 have not been programmed, the programmed code data can be read back via the ad- dress and data lines for verification. ?c0h? command is needed for switching to program verify mode. during pro- gram verify, the code memory use the internally-gener- ated higher margin voltage to the addressed byte. normal verify if lock bits lb2 and lb3 have not been programmed, the programmed code data can be read back via the ad- dress and data lines for verification. if flash command decoder receives the ?00h? command or ic89c52(51)a power is initialized, the command decoder switches to normal verify mode. during normal verify, the code memory use the same threshold as instruction executing threshold. erase verify if lock bits lb2 and lb3 have not been programmed, the programmed code data can be read back via the ad- dress and data lines for verification. ?a0h? command is needed for switching to erase verify mode. during erase verify, the code memory use the internally-generated lower margin voltage to the addressed byte. program lock bit 1, 2, 3 the lock bit 1, 2, 3 is programmed by using the erase command ?60h?, ?70h? and ?80h? in the first cycle. in the second cycle, the ?d0h? command is presented on whole prog strobe time. the prog strobe time is real lock bits programming time. the prog rising edge will clear the erasing state to normal verify state. the programming lock bits operations don?t use the smart algorithm but it is programmed 10 times directly. if programming lock bits are needed, it must be programmed after the encryption array and code memory programming. the ic89c52(51)a lock bits programming flow is described in figure 7. chip erase all flash cell must be programmed to ?00? before the chip is erased. the programming sequence is encryption array, code memory and lock bit 1, 2, 3. the entire flash array is erased electrically by using the erase command ?20h? in the first cycle. in the second cycle, the ?d0h? command is presented on whole prog strobe time. the prog strobe time is real flash erasing time. the prog rising edge will clear the erasing state to normal verify state. the code array is written with all ?1?s. the chip erase operation must be executed before the code memory can be re-programmed. if the any flash cell is not ?1? (include encryption array and lock bits) repeat erase condition less than 50 times. the ic89c52(51)a detail erase flow is described in figure 8. reading the signature bytes: the signature bytes are read by the same procedure as a normal verification of locations 030h, 031h and 032h, except that command is ?90h?. the values returned are: (030h) = d5h indicates manufactured by icsi (031h) = 52h indicates ic89c52a/ic89c51a (032h) = aah indicates programming voltage is 12v 55h indicates programming voltage is 5v the signatures can be read by following conditions. it?s easier to recognize by programmer. 1. rst = high level. psen = low level. prog = high level. vpp = high level. p2.6 = low level. p2.7 = low level. p3.6 = low level. p3.7 = low level. 2. address is switched to (030h), (031h) and (032h). then the data bus outputs the d5h, 52h, aah (55h). program lock bits protection type lb1 lb2 lb3 1 u u u no program lock feature enabled. 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the flash is disabled. 3p p u same as 2, also verify is disabled 4p p p same as 3, also external execution is disabled lock bits features
ic89c52(51)a 10 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 figure. 6 ic89c52(51)a main memory programming flow start programming plscnt=0, address=0, setup received command mode (1) vpp=vppl, setup ?40h? command setup ?c0h? command vpp=vppl, address=0 p2.6 set low pulse for 100 ns p2.6 set low pulse for 100 ns programming error programming completed setup address ,data vpp=vpph orvppl (2) setup address & p2.7 = 0 read data & set p2.7=1 prog set low pulse for 200 us inc address inc address inc plscnt last address ? plscnt=10? verify data? no no no yes yes 1. received command mode status: rst=1, psen=0, prog=1, vpp=1, p2.6=1, p2.7=1, p3.6=1, p3.7=1 2. the vpp voltage is decided by signature byte address(032h) yes yes no last address?
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 11 mc008-0c 11/27/2001 figure. 7 ic89c52(51)a lock bits programming flow start programming plscnt=0, setup received command mode (1) setup ?60h?(?70h? ,?80h?)command p2.6 set low pulse for 100 ns prog set low pulse for 100 ns programming completed setup ?d0h? command vpp=vpph or vppl (2) vpp=vppl plscnt=10? 1. received command mode status: rst=1, psen=0, prog=1, vpp=1, p2.6=1, p2.7=1, p3.6=1, p3.7=1 2. the vpp voltage is decided by signature byte address(032h) no yes
ic89c52(51)a 12 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 figure. 8 ic89c52(51)a erase flow start erase flow plscnt=0, setup received command mode (1) programming all data to ?00? (4) plscnt=0, address=00h setup ?a0h? command p2.6 set low pulse for 100 ns setup address & p2.7 = 0 read data & set p2.7 = 1 inc plscnt erase operation (2) erase operation (2) * 2 pulse erase completed inc address data=?ff? ? no no no yes yes yes 1. received command mode status: rst=1, psen=0, prog=1, vpp=1, p2.6=1, p2.7=1, p3.6=1, p3.7=1 2. the erase operation show in "erase operation" sub-flow 3. to program main memory to '00', then program lock bits. the pre-programming address range are from 0 to 1fffh either in ic89c52a or in ic89c51a 4. the vpp voltage is decided by signature byte address(032h) start erase operation vpp=vppl, setup ?20h? command setup ?d0h? command, vpp=vpph or vppl (5) p2.6 set low pulse for 100 ns vpp=vppl prog set low pulse for 200 ns erase completed chip erase sub-flow chip erase main flow last address ? plscnt=50 ? erase error
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 13 mc008-0c 11/27/2001 operating range (1) range ambient temperature v cc oscillator frequency commercial 0c to +70c 5v r 10% 3.5 to 40 mhz note: 1. operating ranges define those limits between which the functionality of the device is guaranteed. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd (2) ?2.0 to +7.0 v t bias temperature under bias (3) 0 to +70 c t stg storage temperature ?65 to +125 c p t power dissipation 1.5 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. minimum dc input voltage is ?0.5v. during transitions, inputs may undershoot to ?2. 0v for periods less than 20 ns. maximum dc voltage on output pins is vcc + 0.5v which may overshoot to vcc + 2.0v for periods less than 20 ns. 3. operating temperature is for commercial products only defined by this specification. warning: stressing the device beyond the ?absolute maximum rating? may cause permanent damage. this is stress rating only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability.
ic89c52(51)a 14 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 dc characteristics (ta=0c to 70c; vcc=5v +10%; vss=0v ) symbol parameter test conditions min max unit v il input low voltage (all except ea ) ?0.5 0.2vcc ? 0.1 v v il 1 input low voltage ( ea ) ?0.5 0.2vcc ? 0.3 v v ih input high voltage 0.2vcc + 0.9 vcc + 0.5 v (all except xtal 1, rst, ea ) v ih 1 input high voltage (xtal 1, ea ) 0.7vcc vcc + 0.5 v v sch + rst positive schmitt-trigger 0.7vcc vcc + 0.5 v threshold voltage v sch ? rst negative schmitt-trigger 0 0.3vcc v threshold voltage v ol (1) output low voltage iol = 100 a ? 0.3 v (ports 1, 2, 3) i ol = 1.6 ma ? 0.45 v i ol = 3.5 ma ? 1.0 v v ol 1 (1) output low voltage i ol = 200 a ? 0.3 v (port 0, ale, psen )i ol = 3.2 ma ? 0.45 v i ol = 7.0 ma ? 1.0 v v oh output high voltage i oh = ?10 a 0.9vcc ? v (ports 1, 2, 3, ale, psen ) vcc = 4.5v-5.5v i ol = ?25 a 0.75vcc ? v i ol = ?60 a 2.4 ? v v oh 1 output high voltage i oh = ?80 a 0.9vcc ? v (port 0, ale, psen ) vcc = 4.5v-5.5v i oh = ?300 a 0.75vcc ? v i oh = ?800 a 2.4 ? v i il logical 0 input current (ports 1, 2, 3) v in = 0.45v ? ?50 a i li input leakage current (port 0) 0.45v < v in < vcc ?10 +10 a i tl logical 1-to-0 transition current v in = 2.0v ? ?650 a (ports 1, 2, 3) r rst rst pulldown resister v in =0v 50 300 k ? note: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port port 0: 26 ma ports 1, 2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink greater than the listed test conditions. 2.the icc test conditions are shown below. minimum v cc for power down is 2 v.
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 15 mc008-0c 11/27/2001 power supply characteristics symbol parameter test conditions min max unit icc power supply current (1) vcc = 5.0v active mode 12 mhz ? 20 ma 16 mhz ? 26 ma 20 mhz ? 32 ma 24 mhz ? 38 ma 32 mhz ? 50 ma 40 mhz ? 62 ma idle mode 12 mhz ? 5 ma 16 mhz ? 6 ma 20 mhz ? 7.6 ma 24 mhz ? 9 ma 32 mhz ? 12 ma 40 mhz ? 15 ma power-down mode v cc = 5v ? 100 a note: 1. see figures 9,10,11, and 12 for icc test conditiions. figure 9. active mode figure 10. idle mode figure 11. power-down mode (vcc=2.0v~6.0v) xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 vcc xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 xtal1 gnd nc rst vcc p0 ea vcc vcc icc xtal2
ic89c52(51)a 16 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 figure 12. clock signal waveform for i cc tests in active and idle mode (t clch =t chcl =5 ns) ac characteristics (ta=0c to 70 c; v cc =5v r 10%; v ss =0v; c1 for port 0, ale and psen outputs=100pf; c1 for other outputs=80pf) external memory characteristics 24 mhz 40 mhz variable oscillator clock clock (3.5 - 40 mhz) symbol parameter min max min max min max unit 1/t clcl oscillator frequency ? ? ? ? 3.5 40 mhz t lhll ale pulse width 68 ? 35 ? 2t clcl ?15 ? ns t avll address valid to ale low 26 ? 10 ? t clcl ?15 ? ns t llax address hold after ale low 31 ? 15 ? t clcl ?10 ? ns t lliv ale low to valid instr in ? 147 ? 80 ? 4t clcl ?20 ns t llpl ale low to psen low 31 ? 15 ? t clcl ?10 ? ns t plph psen pulse width 110 ? 60 ? 3t clcl ?15 ? ns t pliv psen low to valid instr in ? 105 ? 55 ? 3t clcl ?20 ns t pxix input instr hold after psen 0? 0? 0 ? ns t pxiz input instr float after psen ?37 ?20 ? t clcl ?5 ns t aviv address to valid instr in ? 188 ? 105 ? 5t clcl ?20 ns t plaz psen low to address float ? 10 ? 10 ? 10 ns t rlrh rd pulse width 230 ? 130 ? 6t clcl ?20 ? ns t wlwh wr pulse width 230 ? 130 ? 6t clcl ?20 ? ns t rldv rd low to valid data in ? 157 ? 90 ? 4t clcl ?10 ns t rhdx data hold after rd 0? 0? 0 ? ns t rhdz data float after rd ?78 ?45 ? 2t clcl ?5 ns t lldv ale low to valid data in ? 282 ? 165 ? 7t clcl ?10 ns t avdv address to valid data in ? 323 ? 190 ? 8t clcl ?10 ns t llwl ale low to rd or wr low 105 145 55 95 3t clcl ?20 3t clcl +20 ns t avwl address to rd or wr low 146 ? 80 ? 4t clcl ?20 ? ns t qvwx data valid to wr transition 26 ? 10 ? t clcl ?15 ? ns t whqx data hold after wr 31 ? 15 ? t clcl ?10 ? ns t rlaz rd low to address float ? 0 ? 0 ? 0 ns t whlh rd or wr high to ale high 26 57 10 40 t clcl ?15 t clcl +15 ns 0.45v vcc ? 0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ? 0.1
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 17 mc008-0c 11/27/2001 serial port timing: shift register mode 24 mhz 40 mhz variable oscillator clock clock (3.5-40 mhz) symbol parameter min max min max min max unit t xlxl serial port clock cycle time 490 ? 290 ? 12t clcl ?10 ? ns t qvxh output data setup to 327 ? 160 ? 10t clcl ?90 ? ns clock rising edge t xhqx output data hold after 58 ? 25 ? 2t clcl ?25 ? ns clock rising edge t xhdx input data hold after 0 ? 0 ? 0 ? ns clock rising edge t xhdv clock rising edge to ? 284 ? 117 ? 10t clcl ?133 ns input data valid external clock drive characteristics symbol parameter min max unit 1/t clcl oscillator frequency 3.5 40 mhz t chcx high time 10 ? ns t clcx low time 10 ? ns t clch rise time ? 10 ns t chcl fall time ? 10 ns symbol parameter min max unit vcc programming and erase power voltage 5.25 5.75 v vpp programming and erase enable voltage 11.5 12.5 v ipp programming and erase enable current - 2.0 ma tdvcl data valid to command setup low 10 - ns tclch command setup width 100 - ns tchdx data hold after command setup 10 - ns tavgl address setup to prog low 20 - ns tghax address hold after prog 20 - ns tdvgl data setup to prog low 20 - ns tghdx data hold after prog 20 - ns tshgl vpp setup to prog low 10 - us tghsl vpp hold after prog 10 - us tglgh prog pulse width in programming cycle 200 - us tglghe prog pulse width in erase cycle 200 - ms tavqv address valid to data valid - 50 ns telqv enable low to data valid - 50 ns taxqx data float after address float 0 - ns tehqx data float after enable 0- ns flash program/erase and verification & test mode characteristics
ic89c52(51)a 18 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 figure 14. external data memory read cycle timing waveforms t lhll ale t avll t llpl t plph t pliv t llax t plaz t pxiz t pxix a7-a0 instr in a7-a0 t lliv t aviv psen port 0 port 2 a15-a8 a15-a8 t lldv t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl t avdv psen port 0 port 2 ale rd data in a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t rlaz t rldv t rhdz t rhdx t rlrh figure 13. external program memory read cycle
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 19 mc008-0c 11/27/2001 figure 15. external data memory write cycle figure 16. shift register mode timing waveform t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl psen port 0 port 2 ale wr data out a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t qvwx t whqx t wlwh instruction ale clock data out data in t xlxl t xhqx t qvxh t xhdv t xhdx valid valid valid valid valid valid valid valid set ti set ri 78 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ic89c52(51)a 20 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 figure 17. programming timing wavform p2.4-p2.0 p1.7-p1.0 prog vpp t avgl t dvcl t clch t clch t elqv t ehqx t glgh t ghsl t shgl t chdx t dvgl t ghdx t dvcl t chdx t ghax t avqv t axqx address in address in program setup cycle program cycle program verify setup cycle program verify cycle data out p0 p2.6 (command setup) p2.7(oe) data in 40h c0h
ic89c52(51)a i nt egrat ed ci rc u i tsol ut i on i nc. 21 mc008-0c 11/27/2001 figure 18. erase timing waveform figure 19. external clock drive waveform figure 20. ac test point note: 1.ac inputs during testing are driven at vcc-0.5v for logic ?1? and 0.45v for logic ?0?. timing measurements are made at vih min for logic ?1? and max for logic ?0?. 0.45v vcc ? 0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ? 0.1 vcc - 0.5v 0.45v 0.2vcc + 0.9v 0.2vcc - 0.1v p2.4-p2.0 p1.7-p1.0 prog vpp t dvcl t clch t clch t elqv t ehqx t glghe t ghsl t shgl t chdx t dvgl t ghdx t dvcl t chdx t avqv t axqx address in erase setup cycle erase cycle erase verify setup cycle erase verify cycle data out p0 p2.6 (command setup) p2.7(oe) d0h 20h a0h
ic89c52(51)a 22 i nt egrat ed ci rc u i tsol ut i on i nc. mc008-0c 11/27/2001 ordering information commercial range: 0c to +70c speed order part number package 12 mhz ic89c52(51)a-12pl plcc ic89c52(51)a-12w 600mil dip ic89c52(51)a-12pq pqfp 24 mhz ic89c52(51)a-24pl plcc ic89c52(51)a-24w 600mil dip ic89c52(51)a-24pq pqfp 40 mhz ic89c52(51)a-40pl plcc ic89c52(51)a-40w 600mil dip ic89c52(51)a-40pq pqfp i nt egrat ed ci rc u i tsol ut i on i nc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw

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